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RM -Senior RTL Designers
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RM -Senior RTL Designers
RM -Senior RTL Designers
11 Jun 2024
California
,
Menlopark
,
94303
Menlopark
USA
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RM -Senior RTL Designers
Vacancy expired!
RESPONSIBILITIES
Contribute to the development of efficient Architectures and contribute to ASIC Architecture, design and verification
Understand our in-house IPs needed and how they need to be integrated, connected and verified
Drive the top-level Architecture definition and develop the necessary RTL
Drive the chip-level integration, verification plan development and verification
Supervise the RTL-to-GDS flow and assist with synthesis and timing closure
Support the test program development, chip validation and chip life until production maturity
Work with FPGA engineers to perform early prototyping
Support hand-off and integration of blocks into larger SOC environments
Assist with Algorithm analysis, verification and improvement
Contribute to ASIC digital architecture, design and verification
Ability to communicate clearly
MINIMUM QUALIFICATIONS
10+ years of experience as a Digital Design Engineer and/or a Chip Lead
5+ years of experience in uP and/or GPU and/or Video Processing
Experience in RTL coding, synthesis and/or SoC Integration
Experience in digital design Architecture
BS Electrical Engineering/Computer Science or equivalent experience
PREFERRED QUALIFICATIONS
System Verilog OVM/UVM experience
Python (or similar) scripting experience
Experience in SoC integration and ASIC architecture
Experience in DFT/Testability requirement and test program definition
Experience using High Speed interfaces like PCIe, USB, MIPI
Master's degree in EE
Job Details
ID
JC15345136
State
California
City
Menlopark
Job type
Contract
Salary
N/A
Hiring Company
Experis
Date
2021-06-11
Deadline
2021-08-10
Category
Art/media/design
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