Hardware Test Engineer

Hardware Test Engineer

02 Mar 2024
California, Milpitas, 95035 Milpitas USA

Hardware Test Engineer

Vacancy expired!

US Tech Solutions is seeking Hardware Test Engineer for a 06 months month contract position with a client in Milpitas, CA


Job Poster: MD Umar



Description:

  • Must have great EE fundamentals, FPGA design and analog design and SI experience to support everyday design/validation challenges
  • test and validate switching power supply designs
  • Test and validate signal integrity of interfaces, clocks and peripheral interfaces.
  • define interfaces for FPGA partitioning, design flexible system clocking and reset scheme based on controller specification
  • Define Hardware system architecture of new platforms and perform concept review with development teams
  • Schematics design, manage high density PCB layout design, prototype bring-up and debugging
  • Test and validate NAND, DDR4, PCIe, processors
  • Conduct and review EVT and DVT of different parts of the design and at system level.
  • Ability to communicate with other groups such as Architecture group, ASIC design, FPGA design, Firmware team, program management. Platform related engagement with Procurement, CMs and Finance teams.
  • Lab debug and guiding technicians for rework
  • Rack infrastructure planning and deployment

Job Responsibilities

  • Minimum 8-10 years’ experience in board design at component, board, and system levels.
  • Must have experience with schematic capture software (OrCAD) and Layout (Allegro).
  • Must have clear understanding of fundamentals for DFT and DFM.
  • Experience in high speed interface design ( DDR-4, PCIe, SAS, SATA etc.).
  • Practical experience in hardware debug - use of test equipment (Oscilloscope, Logic Analyzer, Chipscope etc.).
  • Must have HW experience designing high density FPGA boards
  • Must have hands-on experience in prototype bring-up and debugging, functional verification and hardware support/sustenance
  • Experience in small embedded systems, and basic processor and DRAM bringup
  • Experience with development platforms is a definite plus
  • Basic software development experience using C and/or Linux (Perl/Shell scripting) is a plus
  • Experience with Synplify Premier, Identify debugger, Xilinx Vivado, Xilinx ILA, ARM ICE debuggers
  • High level RTL design experience for FPGAs is definitely a plus.

Work experience
  • Minimum 8-10 years’ experience in board design at component, board, and system levels.

Education
  • Bachelor's/Master's degree in Electrical Engineering, or related technical degree is required.


About US Tech Solutions:

Your talent, our opportunities - This is the premise behind US Tech Solutions.
You have the skill we have the opportunity. As a team, we work passionately for you to get the right career opportunity across industry verticals and functions. For past sixteen years, leading Global
Companies and Fortune 500 come to us to get the right talent. Whether you want to work as full-time, contractor or part-time, technical or non-technical our talent consultants will connect with the right career opportunity globally.
Connect with our talent team today.
USTECH was founded in 2000 by Manoj Agarwal. Today, we are a global firm offering talent solutions to 150 customers including 20% of Fortune 500 across Financial Services, Healthcare, Life Sciences, Aerospace, Energy, Retail, Telecom, Technology, Manufacturing, and Engineering. We are headquartered in New Jersey with 40 global locations across the USA, Canada, Europe, and India. Deloitte has recognized USTECH as one of the fastest growing private businesses for the past five consecutive years and INC 500 for the past three. We have also been rated “The Top Business in the US" by Diversity Business since 2011. To learn more about how US Tech Solutions visit our website: www.ustechsolutions.com.

“US Tech is an Equal Opportunity Employer" and “s & all other parties authorized to work in the US are encouraged to apply."

Apply: Interested candidates are requested to send their resume to MD Umar at

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