BSEE in electrical engineering with desired experience in analog/mixed signal IC layout is preferred.
RF Analog with 7nm experience ( approx. 5 years' experience will be good to have ).
OR RF Analog with finFet experience ( approx. 5-7 years' experience )
OR RF Analog with no finFet experience ( approx. 10 years' experience
OR Mix signal with 7nm or other advanced node experience. ( approx. 5- 7 years' experience)
Responsibilities:
In a multi-site project team, you are working on the layout of mobile RF transceiver IC's for our client's cellular (4G/5G) and Connectivity (WiFi/Bluetooth/GNSS) chipsets and SoC.
Full custom layout and verification at block level and top-level chip designs
Chip floor planning, pin placement and die area management, Pad ring layout and ESD insertion, full-chip physical verification, tapeout, and mask data verification
Quickly interpret and repair complicated LVS and DRC problems using state of the art verification software
Work closely under the supervision of IC designers to iterate designs based on parasitic extraction
Required skills/tools:
10 or more years of experience in RF or analog IC layout.
Understanding of layout techniques for design-for-manufacture in deep sub-micron and finFET processes is preferred
Prior work experience with Cadence and a good familiarity with physical verification tools (Assura or Calibre)
Understanding of the physical reason being Design Rule Checks, Layout versus Schematics verification and other physical and electrical design rules.
Good working knowledge of UNIX/Linux and scripting languages (TCL, c-shell, Perl)
Location:
San Diego (CA)
Palo Alto (CA)
Contact:
This job and many more are available through The Judge Group. Find us on the web at www.judge.com
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