Sr. Digital Design Verification Engineer at San Diego CA/San Jose/Austin TX (Minimum 4 years)
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Location:San Diego CA/San Jose CA/Austin TX • 5-15 year’s industry experience in a design verification role. • Proficient in System Verilog/UVM/OVM, OOP/C • Knowledge of GPU, experience with Shader, Texture, or Memory System a plus • Experience with code coverage and functional coverage driven verification methodology. • Experience in creating, running and debugging of SystemVerilog/UVM constraint-random Testbench. • Excellent working knowledge of scripting languages such as Python or Perl.
TrellisWare launched in 2000 with an innovative culture striving to push technological boundaries in the area of wireless communications. We are now a worldwide leader in highly advanced algorithms, waveforms, and communications systems that range from small form factor radio products to fully integrated solutions.
