Please find an urgent requirement Full time. Please respond ASAP with your profile @
Job Title: Design Verification of SOC Location: San Francisco., CA Type: full time
Skills in ASIC / FPGA verification (directed test or SystemVerilog / UVM) Basic knowledge in design techniques Verilog or VHDL A good knowledge of simulation flow Good basis in scripting Python, Perl, Bash… A good level in English, both writing and oral skills
Humanly, you have to be rigorous and have a good analytical mind, you have to enjoy working in a team and being diplomatic, in particular when you have to point out the bugs discovered. Thanks & Regards Hardeep Kamboj Senior Technical Recruiter RADIANSYS INC DeskEXT 1003 Cell: Email :-
