Principal Verification UVM Engineer for leading semiconductor company in the Bay Area
Summary: Seeking Principal Verification Engineer to join Security team to lead verification of secure ASIC cores through collaboration with cross functional teams. Responsibilities:
Design and implement verification methodologies, test plans, testbenches, infrastructure, and platforms
Work with ASIC designers and architects to produce thoroughly verified, robust IP
Architect IP productization, quality assurance, and release automation flows
Lead bring-up and debug of hardware projects (FPGA and post-Silicon)
Lead the verification of secure ASIC cores developed by RSD
Work with cross functional teams including; ASIC design engineers and architects, other verification engineers, security experts, and cryptographers
Required Skillsets:
BS or MS degree in electrical or computer engineering or closely related degree strongly preferred; but substantial, relevant, outstanding work experience may substitute in some cases
Ten or more years of experience working as a verification engineer or related field
Strong written and verbal communication skills: Ability to explain complex concepts in front of technical audience
Strong desire to take ownership of all verification aspects of a project, including team and methodology leadership
High technical competence that includes a track record of effective verification of complex digital designs.
Solid understanding of standard ASIC verification techniques, including:
Test planning
Testbench creation
Code and Functional coverage
Directed and random stimulus generation
Assertions
Solid understanding of verification methodologies, especially UVM
Comfortable in a Unix development environment (make, scripting, SVN, etc.)
Familiarity with advanced verification techniques such as fault/stimulus injection, FPGA prototyping, and/or formal verification
