Design Verification Engineer

Design Verification Engineer

14 Apr 2024
California, Sanjose, 95113 Sanjose USA

Design Verification Engineer

Vacancy expired!

Job Description:
    • Create verification plans for both block level and SoC level verification
    • Create testbenches in SystemVerilog with OVM/UVM
    • Utilize advanced verification techniques
    • Write tools and scripts in Perl and other script languages to enhance the verification process

Qualifications and requirements:
    • BS, MS or PhD in computer science or engineering
    • Experience with SystemVerilog and OVM/UVM
    • Experience with one or more simulators from the major EDA suppliers (Cadence, Mentor or Synopsys)
    • Experience with standard IP blocks and protocols such as Ethernet, TCP/IP, IPSec, iSCSI, DDR3, PCIe
    • Experience with advanced verification techniques like constrained random generation, functional coverage, assertions and formal verifiers
    • Experience with tools for regression management, configuration management and bug tracking
    • Good software skills in object oriented programming (OOP), C, C, Perl, csh
    • Good problem solving

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Job Details

  • ID
    JC12220568
  • State
  • City
  • Job type
    Permanent
  • Salary
    DOE
  • Hiring Company
    Synapse Design
  • Date
    2021-03-18
  • Deadline
    2021-05-17
  • Category

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