ASIC Verification (UVM) engineer

ASIC Verification (UVM) engineer

04 Apr 2022
California, Sanjose, 95101 Sanjose USA

ASIC Verification (UVM) engineer

Vacancy expired!

Series B funded startup 20+ million, working on security management chips and cores to prevent hackers. Great equity options, blue cross blue shield- health insurance.

This Jobot Job is hosted by: Barrett Davis
Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume.

A bit about us:

A security processor company redefining hardware root of trust with hardware-based security technologies, including per-system AI.

Why join us?

Great product working on Security system processors and is an AI-powered engineer to prevent hackers. Great equity options based on experience, and working with a strong team in the bay area.

Job Details

ASIC Verification, UVM, System Verilog
Located in San Jose, California.

Full job description is below.

Senior RTL/SoC Subsystem Verification Engineer position is your opportunity to join one of the industry's leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT.

You should have prior knowledge and experience with UVM verification and UVM environment development.

You will be responsible for RTL SoC/Subsystem verification of ARM based CPUs, and work on industry-standard verification methodologies like UVM, Portable Stimulus and Formal verification flows. You will report to the Director of Engineering, Verification.

KEY RESPONSIBILITIES

Project Leadership

Help develop test plan definition and development;
Micro-architecture design verification, RTL verification, and documentation;
Top-level and block-level performance verification, power, and use-case verification; and
Support test program development, chip validation, and chip life until production maturity.
Team Management and Building

Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.
Qualifications
5+ years of experience in UVM verification and UVM environment development;
Proficient in testplan definition and testcase development in C/Assembly/SystemVerilog;
Expertise in verifying design at RTL level and gate-level simulation;
Good understanding of coverage analysis, performance verification and use-case verification;
Experience in functional test vector development and post-silicon bring-up/debug;
Fluency with scripting languages (e.g., Perl, Python, Shell); and
Preferred: knowledge of Power Aware verification is a plus.

Interested in hearing more? Easy Apply now by clicking the "Apply Now" button.

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Job Details

  • ID
    JC37677764
  • State
  • City
  • Job type
    Permanent
  • Salary
    Based on Experience
  • Hiring Company
    Jobot
  • Date
    2022-04-03
  • Deadline
    2022-06-02
  • Category

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