Verification Engineer

Verification Engineer

21 Jan 2024
California, Santaclara, 95050 Santaclara USA

Verification Engineer

Vacancy expired!

Position:VerificationEngineer
Location:Santa Clara CA (
Initially this position would start asREMOTE/ Telecommutework due to COVID situation but eventually when the COVID restrictions willbe lifted, this would goONSITEin Santa Clara CA)
Format: Full Time
Description:

  • Develop test benches in UVM, SystemVerilog, Verilog, C, C and other languages.
  • Write test plans for digital signal processing logic blocks, control logic blocks, general-purpose processor cores and other digital logic devices.
  • Write and debug tests for a complex media processor in UVM, SystemVerilog, Verilog, C, C, Perl, Python and other languages.
  • Developverificationtools.
  • Perform coverage analysis using CAD tools.
  • Perform system-levelverificationof Ambarella's Video Input block as well as other blocks.
  • Perform BlockVerificationof Ambarella's very complex CABAC compression block.

Requirements:
  • You must possess a MSEE/CE degree.
  • Knowledge of video compression and decompression algorithms.
  • Knowledge of different types of memories and memory subsystems; e.g., DDR4, LPDDR3, LPDDR4.

.
Regards,
Sam Aaron
+1

E-Solutions Inc.

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