System Validation Engineer

System Validation Engineer

02 Jan 2024
California, Westmenlopark, 94025 Westmenlopark USA

System Validation Engineer

Vacancy expired!

Responsibilities:
  • Writing CPP System Level tests targeting the CPU/DSP/CNN cores in CPP
  • Writing CPP Performance and Power system-level use-cases
  • Work on FPGA and Emulation scripts and flows for system validation, to increase productivity across the team
  • Work on post-silicon bringup and flows
  • Work closely with Algorithm engineers, DV engineers, Architects and Designers to come up with system level use-case scenarios
  • Work closely with Design Verification to enhance and augment verification for IPs on FPGA and/or Emulation platforms
  • Work closely with Firmware, Reference Modeling, and Software engineers to assist software development and debug

Skills:

What are the must have non-negotiable requirements for this role?
  • Experience in CPP for writing system level test-cases for SoC like IP
  • Experience in scripting languages such as Python, TCL etc
  • Experience running tests on FPGA and/or Emulation platforms for SoC like IP
  • Experience in post-silicon bringup and flows for SoC like IP
  • Experience with lab system debug with logic analyzers, scopes, meters, etc
  • Experience in performance evaluation and modeling for SoC like IP
  • Experience in power tests and evaluation on prototyping platforms
  • Familiarity with AMBA protocol, OCP protocol
  • Familiarity in System Verilog for design and verification - for debugging

What are the nice to have details for this role?
  • Performance modeling and evaluation
  • Knowledge of OS kernel and experience in driver development
  • Familiarity with IO’s such as MIPI CSI & DSI, USB, PCIE, LPDDR

Job Details

  • ID
    JC7695938
  • State
  • City
  • Job type
    Contract
  • Salary
    Depends on Experience
  • Hiring Company
    DISYS - Digital Intelligence Systems, LLC
  • Date
    2020-12-31
  • Deadline
    2021-03-01
  • Category

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