Senior Principal Engineer, PD Expert (MCU and derivative devices)

This role is a senior technical authority responsible for defining, aligning, and governing Physical Design Architecture, Technology aspects, Foundry selection & PPA. The technologist serves as the primary interface between the internal SoC Physical Design organization and the foundry, systems team  & ensure competitive edge.Foundry (TSMC) Interface & OwnershipPrimary technical point of contact with TSMC for Physical Design.Technical discussions with foundry team internal and external with regards to foundry selectionWork with foundry & technology to define requirements for signoff & collaterals.AI InitiativeLead an AI initiative focusing cost reduction of MCU developmentDrive the AI strategy of Physical team in conjunction with methodology teams and external vendors. Pilot AI initiatives within organization including scoping, definition & implementation.Physical Design Architecture Definition and FeasibilityWork with system architects, Architecture team & Chip leads to ensure physically realizable architecture for MCU designsDrive Physical Partitioning, latency, pipeline planning, IO & AC requirement with leads. Align Die-size & PPA targets & KPI for SoC/MCUs