Design Verification Engineer -San Jose, CA ; Austin, TX; Remote
Vacancy expired!
Hi, Hope you are doing good. We do have a Design Verification Engineer role in San Jose, CA; Austin, TX; Remote. Please go through the job description and kindly reply with your updated resume.
Role: Design Verification Engineer Job Location: San Jose, CA; Austin, TX; Remote Duration: 12+ Months JOB DESCRIPTION As a Contract Design Verification Engineer, you will contribute to the functional verification of GPU IP. This is a hands-on role, driving next generation product development with a high level of contribution and knowledge base needs.
Key responsibilities may include:
GPU top level verification test plan development and execution:
Work with RTL and unit level DV teams to develop test plans.
C, SV/UVM stimulus development using constrained random and directed test flows.
Functional coverage development and overall coverage closure.
Develop and maintain SV/UVM components for GPU top level test bench and flows.
Debug, maintain and track GPU level functional regressions.
Support SOC, emulation, and silicon teams in debugging functional failures.
Minimum requirements:
BSEE, Computer Engineer or comparable and 5 + years of DV experience
Advanced knowledge of GPU and/or CPU architecture.
Experience with SV/UVM, C, Verilog, Verdi, and coverage flows.
Experience with debugging in a full CPU or GPU top-level design.
Proficiency with scripting languages (Python, Perl).
Excellent communication skills and ability to work with cross-functional teams.
