Looking for an experienced senior verification engineer to participate in the following activities:
Understand complex architecture spec and develop a new testplan / review existing test-plans to provide feedback on missing test-cases
Reviewing Architecture and Microarchitecture specs to identify holes
Systemverilog and UVM expertise for developing a testbench
Multiple years of experience in development of testbench, running/debugging tests, driving coverage closure
Possibility of working with Formal Verification Tools
Skills required:
Experienced with verification SoC/block level verification and has vast experience in testplan development
Recent experience in SystemVerilog based testbench development and has a good hold on SystemVerilog coding
Strong verification mindset for developing testplans by reading a hardware specification
Experienced with Formal Verification Tools such as SLEC
Desired:
Perl/python scripting (nice to have)
#Dice-SPG
#Zip-SPG
#Mon-SPG
#CB-SPG
#IND-SPG
Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
Visit https://www.yoh.com/applicants-with-disabilities to contact us if you are an individual with a disability and require accommodation in the application process.