Remote Job Opening - Verification Engineer - Chandler, Arizona

Remote Job Opening - Verification Engineer - Chandler, Arizona

02 Mar 2021
Arizona, Chandler, 85226 Chandler USA

Remote Job Opening - Verification Engineer - Chandler, Arizona

Description: Responsibilities & Duties:

Please note: This role will be remote for now, but will move to on-site once COVID restrictions are lifted.

A Pre-Si Verification Engineer position is available within the Data Center Power Solution group. This group works with Intel silicon, package and board design teams to deliver leading edge power solutions. The successful candidate will be a key contributor to the pre-silicon functional verification of state-of-the-art power management ICs.

Your responsibilities will include but not be limited to:
1. Design and Pre-Silicon verification with experience leading Verilog digital behavioral modeling of mixed-signal and analog systems, prefer experience working with PMIC (Power Management IC's)
2. RTL design with experience leading implementation of controller for mixed-signal chips
3. Experience in developing synthesizable accelerated analog behavioral models for representing SVID, VR, PMIC behavior in Pre-Silicon SOC/ASIC environments
4. Take ownership of Pre-Silicon functional verification of subsystems and/or complete chips
5. Determine whether anomalous symptoms are caused by errors in the specifications, models, test bench or design
6. Write verification plan
7. Write and maintain behavioral models and test benches in Verilog
8. Write technical documentation and presentation

Qualifications & Experience
1. Functional design verification mixed-signal integrated circuits for power management applications
2. Excellent understanding of power management IC's
3. RTL design and coding expertise using Verilog and/or VHDL for validation and testing digital circuits
4. Ability to create and evaluate synthesis/build and simulation tool flows
5. Digital design and Pre-Si verification with experience leading Verilog digital behavioral modeling of mixed-signal and analog systems, specifically SVIDs, VRs, and PMICs
6. Developing synthesizable accelerated analog behavioral models representing PMIC behavior in Pre-Silicon SOC/ASIC environments
7. Experience validating externally sourced SVIDs, VRs and PMICs
8. Good English writing and speaking skills

Educational preferences included BSEE with 10 years of relevant experience, MSEE with 7 years or PhD EE with 3 year

Additional qualifications include:
Strong desire to assume responsibility and to proactively address ambiguities
Strong written and verbal communication skills
Explain and present complex ideas
Work in a dynamic environment and organize effectively
Excellent team player with good interpersonal and teamwork skills
Results oriented
Ability to understand business impact of technical decisions

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Job Details

  • ID
    JC10488797
  • State
  • City
  • Job type
    Contract
  • Salary
    USD $Depends on Experience Depends on Experience
  • Hiring Company
    Infobahn Softworld Inc.
  • Date
    2021-03-02
  • Deadline
    2021-05-01
  • Category

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