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Job DescriptionIn this role, you will collaborate with experts in various technology development sectors, EDA vendors, and product design teams. Your goal will be to develop and deliver top-quality industry-leading memory technology collaterals and to drive circuit innovations, to enable next generation high-performance, high-density, low-power embedded memory designs on Intel's advanced CMOS process technologies.Your responsibilities will include, but may not limited to:
Driving memory bitcell definition and peripheral circuit solutions on Intel's most advanced process technologies.
Defining and implementing design and construction rules for memory components and Macros.
Developing and validating memory libraries for Process Design Kit (PDK) releases.
Pioneering layout automation on memory collaterals, arrays, and peripherals.
Engaging in memory pathfinding activities and optimizing power, performance, and area (PPA) through design technology co-optimization (DTCO).
This is an entry level and compensation will be given accordingly.#DesignEnablementQualificationsYou must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.Minimum Qualification:Candidate must possess a MS degree with 6+ months of experience or PhD degree with 1+ years of experience in Electrical Engineering or Computer Engineering or Electrical and Computer Engineer degree a related discipline.6+ months of experience in the following:
Knowledge of the CMOS ASIC design flow.
Custom digital circuit design, simulation, layout design, and verification.
Knowledge of EDA tools used for analog, digital and mixed-signal circuit design.
Preferred Qualifications:6+ months of experience in the following:
Experience with advanced CMOS process technology and device physics.
Experience in design, characterization, and verification of custom memory circuits such as SRAM, Register Files, ROM, etc.
Experience in physical design optimization on custom circuits.
Experience with design trade-off of power, performance, and area (PPA).
Inside this Business GroupAs the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.Posting StatementAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)Annual Salary Range for jobs which could be performed in US, Colorado, New York, Washington, California: $106,231.00-$159,109.00Salary range dependent on a number of factors including location and experienceWorking ModelThis role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. This role may also be available as our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
