Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Semi and Custom IP team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedication for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.We are looking for a Principal Engineer, Mask Layout to join the team.Responsibilities
Custom SRAM Layout Implementation : Lead the detailed layout of SRAM cells, memory arrays, and peripheral circuits, focusing on achieving optimal placement, routing, and electrical performance for custom designs.
Design Rule Checking (DRC), Layout vs. Schematic (LVS), DFM, Antenna, and SRAM Checkers : Ensure all layout designs adhere to the foundry's design rule checks for manufacturability, perform layout vs. schematic checks to verify that the physical layout matches the circuit design, address design-for-manufacturability and antenna effects, and utilize foundry SRAM checkers to ensure compliance with technology node requirements and improve design reliability.
Optimization : Optimize layout for performance, power, and area, implementing advanced techniques to minimize parasitics and improve overall design efficiency.
Cross-Functional Collaboration : Work closely with circuit designers and other layout designers, both internal and external to the memory team, to understand design requirements and constraints, translating them into efficient layout designs.
Tape-out Readiness : Prepare layout for final tape-out, ensuring all necessary checks and validations are completed.
Technical Leadership and Mentorship : Serve as one of the tech leads with the ability to help drive multiple macros while working closely with the layout manager, providing guidance and mentorship to layout engineers, and fostering a collaborative and innovative environment.
Stay Updated : Keep up with the latest trends and advancements in layout design tools and methodologies.
Embody our Culture (https://www.microsoft.com/en-us/about/corporate-values) and Values (https://careers.microsoft.com/us/en/culture)
QualificationsRequired Qualifications:
9+ years of related technical engineering experience
OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
9+ years of experience in custom SRAM Memory Layout.
9+ years of experience using Calibre and Cadence tools.
Other Requirements:Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings:
Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.
Preferred Qualifications:
Experience with using and setting up Ansys Totem.
Deep knowledge of custom digital layout design.
Expertise in Python, SKILL, or TCL scripting and C programming.
Good communication skills.
Excellent problem-solving skills and creative thinking.
Proficiency with 5nm and/or 3nm technology nodes.
Proven track record of delivering high quality memory layout designs.
Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $137,600 - $267,000 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $180,400 - $294,000 per year.Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-payMicrosoft will accept applications for the role until November 27, 2024.#azurehwjobs#AHSI#SCHIEMicrosoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .
