Role Emulation Engineer (PcIe)
Location - Santa Clara, CA
Open for FTE/Contract
Looking for strong candidates with hands-on experience in adapting example FPGA designs in PCIE/CXL and Ethernet for VCS simulation and hardware checkout using Intel or Xilinx FPGAs. The candidate should have deep knowledge of transaction level protocols and debug thereof from previous projects. Some coding in System Verilog and exposure to test bench development with DPI interfaces with C/C code before targeting the design to FPGA is needed.
"As an emulation engineer, you will be responsible for performing any model related updates , modifications or creating of wrappers etc.
The updated models needs to be integrated in to the build environment and should build the models.
Any build failures needs to be debugged and fixed.
The updated model needs to be validated by taking appropriate tests, test failure needs to be debugged.
Candidate needs to have working knowledge of System Verilog and Verilog as the code development happens with these languages.
They also need to be aware of scripting as they need to integrate the model using scripts and also any kind of automation will involve scripting experience.
Will be majorly working on PCie related protocol hence PCIe working knowledge is a must.