Seeking an FPGA Engineer who has extensive knowledge of digital circuit design, state machines, Boolean math and FPGAs.Candidate shall have experience withCompleting multiple FPGA or ASIC design using Verilog and/or VHDL, including at least one of moderate complexityDemonstrate knowledge and development of a test bench with self-checking and simulation (including back annotated timing) for given FPGA modules, top level FPGA, and system with multiple FPGAsFPGA technology differences (Xilinx vs Actel/Microsemi)FPGA process and development flows, especially flows using Synplify Pro, ISE, Vivado and LiberoScripting languages such as TCL or PythonLeading small sized teams in order to develop moderately complex systems according to program schedule expectationsRequired skillsFPGA design experience including thorough design documentation, completion and review of RTL blocks, participation in code reviews, significant RTL debug, and working knowledge of CDC, reset and clock design Ability to solve digital lab debug problems with use of lab tools such as bench supplies, scopes and logic analyzers Knowledge of RTL design techniques for radiation upset mitigation and experience using multiple RTL languages are a plus.
