ESSENTIAL DUTIES AND RESPONSIBILITIES:Develop, test and support UVM testbenches for SoC level verificationTestplan documentation and code reviewsVerify various features using targeted/random/corner-case/coverage testsSimulate and debug RTL and digital circuits using tools such as Cadence Incisive, Cadence Xcelium, Cadence vManager, Mentor Graphic QuestaSim, and/or Synopsys VCSRegression management and code/functional coverage analysisDevelop, test and support scripts for simulation, regression management, synthesis/timing, documentation and other tools
