Education: Bachelor or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with minimum 9+ years of experienceExperience in architecting digital designs and writing device-level or sub-system specifications.Fluent in Verilog RTL coding and ASIC design methodologyExpertise in digital design implementation, including logical synthesis and DFT insertion with high coverageExperience with static timing analysis and creation of place and route constraintsProficiency in formal verification, linting, and CDC/RDC checkingKnowledge of asynchronous clock crossings and synthesis implications of RTLExperience implementing and verifying ECOs on RTL, synthesized, and post-route netlistsCompetence in developing design constraints for synthesis, STA, and P&R hand-offExperience with gate-level simulations and understanding the causes and implications of timing violationsFamiliarity with ATPG generation and ATE support (a plus)Experience in DFT or physical design (a plus)Experience with UVM and/or SystemVerilog for verification (a plus)
