In this multi-disciplinary role, you will lead the end-to-end delivery of derivative SoCs, focusing on the intersection of RTL design, functional verification, and physical implementation. You will not just execute flows; you will build an AI-augmented "Silicon Factory" that uses machine learning to bridge the gap between architectural intent and GDSII. Your goal is to achieve ultra-fast turnaround times by using AI to predict physical outcomes during RTL coding and to automate the verification of design variants.Key Responsibilities1. AI-Augmented RTL & ArchitecturePhysical-Aware RTL: Use ML-based predictors to evaluate RTL code for timing and congestion bottlenecks before synthesis, reducing the number of "RTL-to-GDS" iterations.Derivative Generation: Develop scripts and Generative AI prompts to automate the creation of RTL wrappers, memory maps, and bus interconnects for design variants.Logic Optimization: Employ AI to identify redundant logic or clock-gating opportunities to hit aggressive power targets in derivative designs.2. Intelligent VerificationAutomated Testbench Scaling: Build AI-driven verification environments that automatically adjust constraints and coverage goals when a design derivative (e.g., changed cache size or port count) is instantiated.Smart Regression Management: Use ML to prioritize test cases that are most likely to fail based on historical RTL changes, slashing simulation time and compute costs.Bug Prediction: Deploy pattern-recognition models to identify "bug-prone" modules in the RTL based on complexity metrics and previous tape-out data.3. Rapid Physical ImplementationSeamless Handoff: Ensure a "zero-friction" path from RTL to Physical Design by using AI to automatically generate floorplan constraints and timing assertions from the design spec.Closure Acceleration: Drive the physical implementation of derivatives, using AI to "reuse" placement and routing solutions from parent designs to achieve 10x faster convergence.
