Minimum qualifications:
Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience.
15 years of experience in a Silicon Physical Design role.
10 years of experience in silicon management.
Experience in lifecycle development and delivery of high-performance silicon products.
Preferred qualifications:
20 years of PD experience in complex processor-class ASIC or SoC programs, including track record of product delivery and deployment.
10 years of experience in managing implementation, PD teams, and working with silicon foundries, memory suppliers (DRAM, HBM, etc.), and test services.
Experience in PD tools, flows, methodology development, and with PD for large die, advanced process nodes, and advanced packaging (2.5D, 3D).
Experience with EDA and third-party IP vendors.
Technical understanding of implementation/PD steps, synthesis, floorplanning, place and route, power/clock distribution, congestion analysis, timing closure, CDC analysis and formal verification on blocks, subsystems or fullchip.
Our computational challenges are so big, complex and unique we have to develop it ourselves. Your organization designs and builds the hardware, software, and networking technologies that power all of Google's services.Manage a COT and ASIC Physical design group primarily responsible for TPU development (DeepSea program). Other programs supported by the team include Video Codecs (Argos) and Networking (Rockstar).As the Engineering Director, Physical Design within Google's hardware team, you will help deliver products that have a substantive impact on the Technical Infrastructure that powers Google. You will play a major role in our Tensor Processing Unit (TPU) roadmap by providing technical and management leadership for our strategic silicon development. The role requires driving complex engineering projects from the concept/planning stage through execution and closure. The US base salary range for this full-time position is $262,000-$377,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google (https://careers.google.com/benefits/) .
Implement physical design of TPUs from concept to tapeout in both ASIC and COT models.
Support product delivery and success through the entire lifecycle.
Bring direct PD and technology ecosystem expertise to bear in product roadmap definition.
Partner closely with other silicon functions as a senior leader in the overall silicon organization.
Engage third-party foundry, ASIC, IP, Memory, and EDA ecosystem.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.
