Design Verification of SOC Engineer

Design Verification of SOC Engineer

18 Jan 2024
California, Sanfrancisco, 94101 Sanfrancisco USA

Design Verification of SOC Engineer

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Role:

Design Verification of SOC Engineer


Location:

San Francisco, CA

| Onsite

Duration: Full-time role

Job Description
Design Verification of SOC
Skills in ASIC / FPGA verification (directed test or SystemVerilog / UVM)
Basic knowledge in design techniques Verilog or VHDL
Good knowledge of simulation flow
A good basis in scripting Python, Perl, Bash…
A good level in English, both writing and oral skills

Humanly, you have to be rigorous and have a good analytical mind, you have to enjoy working in a team and being diplomatic, in particular when you have to point out the bugs discovered.


With Every Good Wish

Vikash Kumar |

RADIANSYS INC
Lead Consulting

WorkExt 1009 |

Cell|

Email:
39510 Paseo Padre Pkwy, Suite 110 Fremont, CA 94538

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Job Details

  • ID
    JC8317222
  • State
  • City
  • Job type
    Permanent
  • Salary
    Depends on Experience
  • Hiring Company
    Radiansys, Inc.
  • Date
    2021-01-15
  • Deadline
    2021-03-16
  • Category

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