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Hi
Hope you are doing good.
Please take a look & let me know your comfort level with the same.
If interested, then do send me the updated copy of your resume along with the best time to reach you.
Look forward to your response.
DV Engineer
San Jose, CA
Job Responsibility
Knowledge of Code coverage using features in existing simulators or stand-alone tools like Surecov, HDL score etc.
Working on full chip verification and OVM/UVM Methodology, System Verilog is a must with 3+years of recent work experience, worked on passing test cases, test benches, Building environment.
Knowledge of Functional coverage using HVL language features or assertions a plus.
Should be ARM based SoC verification only. No need to mention tools.
Proficiency in one scripting language like Perl, C, Python, Unix Make, Unix Shell Scripts etc. Desired Skills & Experience:
Experience level 4+ years.
Strong domain knowledge on one or more - PCIe,USB, Ethernet, ARM, AHB/AXI, AMBA, Networking, CPU, ARM, Graphics (DDR, PCIE, USB)
Should have worked on SOC verification on at least one project with constrained random methodology (OVM/UVM).
Good in concepts Code coverage and functional coverage.
Expertise in Verilog and / or VHDL is desired.
Strong in SV & OOPS
IP or SoC verification
Functional + code coverage
ARM based SoC verification
Capable of developing C tests
Working knowledge - SV/METH
Code coverageEducation: B.Tech/B.E., in Electronics/Telecommunication, Electrical) OR (PG - M.Tech/M.E, in (Electrical, Electronics/Telecommunication)
Thanks and Regards,
Arvind Kaur Gurm
Technical Recruiter
P: : E:
2N Market St, Suite # 400, San Jose, CA- 95113
www.e-solutionsinc.com
linkedin.com/in/arvind-gurm
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Disclaimer:
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