Your CareerAs an ASIC Integration and Physical Design Engineer, you will ensure that the ASICs in our groundbreaking next-generation firewall products meet or exceed industry-leading requirements for performance, reliability, and power efficiency.  You will integrate third-party IPs and PANW designs at the subsystem and top levels.  You will guide the design team on strategies for clocks, resets, and synchronization.  You will collaborate closely with the ASIC vendor and the PANW ASIC design team in floorplanning, closing timing, validating constraints, and optimizing power consumption.Your ImpactIntegrate PANW designs at the subsystem and top levels, ensuring robust solutions for clocks, resets, feedthroughs, and DFT.Integrate RAMs, CAMs, custom IPs, and IO pads throughout the design hierarchy.Collaborate with external ASIC vendors to define optimal floorplans, power grids, clocking strategies, and custom routing.Guide internal RTL designers in closing timing, reducing congestion, optimizing power consumption, and validating constraints.
