Design Verification Engineer

Design Verification Engineer

28 Mar 2024
California, Sunnyvale, 94085 Sunnyvale USA

Design Verification Engineer

Vacancy expired!

Building a test bench for a block using System Verilog and UVM
Writing random tests, directed tests, error tests & performance tests for a block of Verilog and UVM.
Developing, maintaining and supporting of the UVM verification environment.
Debugging tests with design engineers to deliver functionally correct design blocks
writing & analyzing functional coverage, assertions
Generating and analyzing code coverage & writing waivers.

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