Minimum qualifications:
Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
2 years of experience working in a signal integrity technical environment, or 1 year of experience with an advanced degree.
Preferred qualifications:
Master's or PhD degree in Electrical Engineering, Computer Engineering, Physics, or a related field.
Experience with Allegro, ADS, MATLAB, PowerDC, PowerSI, HFSS, SIwave, and CST.
Experience with the product development process for mass volume production design, with a focus on signal integrity and lab validation.
Experience with SerDes testing in a lab setting, and familiarity with PCIE, DDR, SATA, and Ethernet standards.
Familiarity with PCB, connector, and/or cable design and assembly processes, including materials and component selection.
Understanding of SERDES capabilities, and of FEC and its implications for system design.
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.The US base salary range for this full-time position is $122,000-$178,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google (https://careers.google.com/benefits/) .
Manage System Signal Integrity (SI) design on data center hardware products.
Collaborate with board, chip, and system engineers, design partners, and chip vendors to drive system SI design. Explore layout and manufacturability trade-offs, and ensure product functions as needed.
Drive ASIC, package, board, connector, and cable vendors to develop new interconnect technologies.
Manage system interconnect bring-up and qualification, working with test engineers, including configuring chips to ensure adequate margin.
Drive solutions for SI issues with design engineers, PCB designers, and system team. Run trade-off analysis on performance and cost.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.
