Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
5 years of experience with industry-standard tools used in the development of silicon-based ICs and chips.
3 years of experience with digital design experience using SystemVerilog RTL.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
3 years of experience in digital design using SystemVerilog RTL.
Experience in interacting with software, architecture, and other cross-functional teams.
Experience applying computer architecture principles to solve problems.
Knowledge of the fundamentals of Computer Architecture.
Knowledge of processor design, accelerators, or memory hierarchies.
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.As a Tensor Processing Unit (TPU) Compute RTL Design Engineer you will be part of a team developing Application-specific integrated circuit (ASICs) used to accelerate computation in data centers. You will have responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center acceleratorsBehind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.The US base salary range for this full-time position is $150,000-$223,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google (https://careers.google.com/benefits/) .
Work independently to create and review compute subsystem's design microarchitecture specifications.
Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
Work with Design Validation (DV) teams to create testplans to verify and debug design RTL.
Work with physical design teams to ensure design meets physical requirements and timing closure.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.
