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Job DescriptionDo Something Wonderful!The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people’s digital lives. Come join us and do something wonderful!Who We AreWe are the Intel CEG DDR Structural Design team driving the future of DDR technologies with Intel. We deliver custom analog and mixed signal layout designs for current and next generation DDR designs which are used across Intel's spectrum of products, including client CPUs, Server CPUs, and/or other domains.Who You ArePerforms physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. Optimizes design to improve product-level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.QualificationsMinimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications :A Master’s degree in Electrical Engineering or similar AND5+ years of experience in the following:
Synthesis and PNR flows on designs with greater than 500k instances
Expertise in Floorplanning, Clock Tree Synthesis, Placement and Routing for complex Mixed-Signal blocks
Industry standard tools including Fusion Compiler, Primetime, Conformal etc.
Preferred Qualifications:
7+ years of experience in Physical Design
Familiarity with scripting languages Perl, Tcl, Python etc.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.Other LocationsUS, AZ, Phoenix; US, CA, Santa ClaraPosting StatementAll qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)Annual Salary Range for jobs which could be performed in US, California: $123,419.00-$185,123.00Salary range dependent on a number of factors including location and experienceWorking ModelThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
