NAND array algorithm development and performance/reliability engineering.Key Responsibilities:Design, plan, and execute NAND memory cell and array characterization experiments to evaluate performance and reliability.Develop and optimize trims to minimize program and read disturb, directly impacting product quality.Develop and optimize trims to optimize performance and power (tPROGRAM, tREAD, Icc), without impacting reliability and endurance capabilities.Apply NAND device physics principles to explain and interpret relationships between experimental data and trim parameters.Conduct comprehensive data analysis to identify and communicate trade-offs across multiple parameters of interest.Use NAND device physics knowledge and problem-solving skills to design experiments, identify product failure mechanisms, and implement effective solutions.Collaborate cross-functionally with Device, Design, Reliability, and Product/Test Engineering teams to design, test, and deeply innovative method to improve performance and reliability.
